This invention relates generally to clocking circuits on integrated circuits (ICs). More particularly, this invention relates to improving clock frequencies on ICs.
A microprocessor, an example of an IC, used in many large computer systems may include memory elements, combinational logic, and a clocking system. The memory elements may be arranged in sets, sometimes called registers that may correspond to the word size used in a computer system. Between at least some sets of memory elements are combinational logic circuits. At the end of a clock cycle, which is also the beginning of the next clock cycle, data on the output of the combinational logic circuitry is stored in a first set of memory elements. This data appears on the output of the set of memory elements, and therefore on the input of other combinational logic circuitry. The other logic circuitry performs the designed logic function on the data, and at the end of the clock cycle the output of this combinational logic is stored in a next set of memory elements. This process is repeated as the computer operates. In other words, data is processed by combinational logic circuitry, stored in memory elements, and then passed on to other combinational logic circuitry. A system clock, often a PLL (Phase Locked Loop) controls the clocking of information from one state to the next state.
Typically, the period of the system clock can not be shorter than the delay time of the slowest logic path from one memory element to another memory element. When a chip is designed, simulations often give a good estimate of the slowest logic path. However, when a microprocessor, for example, is fabricated, the slowest logic path may be one other than a logic path identified by simulation. In addition, the slowest logic path may be faster or slower than anticipated by simulation.
If the slowest path is faster than anticipated by simulation, the frequency of the system clock may be increased from the original design frequency. If the slowest path is slower than anticipated by simulation, the frequency of the system clock should be decreased or errors will occur.
In order to obtain the maximum system clock frequency for a particular IC, the input of a programmable delay line that approximates the delay of the slowest path on the IC is connected to the system clock. An edge of the output of the programmable delay line is compared to an edge of the system clock by a comparator. The comparator sends a signal to a frequency synthesizer to increase the frequency of the system clock if the edge of the delay line output arrives considerably before the system clock. The comparator sends a signal to a frequency synthesizer to decrease the frequency of the system clock if the edge of the delay line output arrives considerably after the system clock.
The comparator has a programmable dead zone delay circuit centered in time around the system clock. If an edge of the output of the programmable delay line output falls within the dead zone (DZ), the comparator sends a signal to a frequency synthesizer to leave the period of the system clock near its present value.
Metastability occurs in a comparator when an edge of the output of the programmable delay line output arrives near an edge of the dead zone. As a result, a comparator may create a relatively long delay before sending a signal to either increase the period of the clock, decrease the period of the clock, or leave the period of the clock near where it is presently. As a result, the frequency synthesizer doesn""t control the system clock period until this delay is ended. If the delay is too long, the frequency synthesizer will fail in an unrecoverable manner.
Other delays may cause the frequency synthesizer to fail in an unrecoverable manner. For example, route delay may be long enough to cause the frequency synthesizer to fail without recovery. A programmable delay line may also create a delay that is long enough to cause the frequency synthesizer to fail without recovery. For example, if the voltage supplied to the programmable delay line is low enough, the delay created by the programmable delay could be long enough to cause the frequency synthesizer to fail without recovery.
There is a need in the art to eliminate the delay times that can cause a frequency synthesizer to fail. An embodiment of this invention provides a fail-safe system that eliminates any delays long enough to cause the frequency synthesizer to fail without recovery.
In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first phase comparator with at least three inputs and an output is preset to a predetermined logical value by a first control circuit. A second phase comparator with at least three inputs and an output is preset to a predetermined logical value by the first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.